The present invention relates to a semiconductor device in which a capacitive element, a resistor and a transistor are provided.
The (analog-digital) semiconductor device in which a capacitive element and a resistive element are provided in addition to a MOS transistor according to the prior art has been implemented by adding the steps of manufacturing the capacitive element and the resistive element (analog) to the steps of manufacturing an ordinary MOS transistor (digital). In this case, it is desirable that a capacitive element having a great capacitance value per unit area should be formed in order to reduce the area occupied by the capacitive element.
The structure and manufacturing steps of a semiconductor device in which the MOS transistor and a two-layer polysilicon type capacitive element are provided according to the prior art will be described below. FIGS. 8(a) to 8(d) are sectional views showing the manufacturing steps of a semiconductor device in which an n-channel type MOS transistor and a two-layer polysilicon type capacitive element are provided.
As shown in FIG. 8(a), a LOCOS isolation 102 is formed on a part of a p well 101 of a silicon substrate. A region where the surface of the p well 101 is exposed is a region Rtra where a transistor is to be formed. A region Rcap where a capacitive element is to be formed is provided on the LOCOS isolation 102.
As shown in FIG. 8(b), a polysilicon film is deposited in a thickness of 200 nm, for example. Then, a first conductor film into which an impurity is introduced (not shown) by a POC13 diffusion method or the like is deposited to form a first resist film 104 having a desired pattern. Thereafter, the first conductor film is patterned by a dry etching method to form a lower capacitive electrode 103a. 
As shown in FIG. 8(c), a gate oxide film 105 is formed by pyrogenic oxidation in a thickness of 10 nm, for example. At this time, an oxide film is simultaneously formed on the lower capacitive electrode 103a in a thickness of about 20 nm to be a capacitive film 106 (which has a greater thickness than that of the gate oxide film 105 because polysilicon is oxidized more quickly than single crystal silicon). Then, a second conductor film (not shown) made of a polysilicon film having a thickness which is almost the same as that of a first conductor film 103a is formed on the LOCOS isolation 102, the gate oxide film 105 and the capacitive film 106. Consequently, a second resist film 109 having a desired pattern is formed on the second conductor film. By using the second resist film 109 which covers a part of the region Rtra and a part of the first conductor film 103a of the region Rcap, a second conductor film is patterned by the dry etching method to form a gate electrode 107a in the region Rtra and an upper capacitive electrode 107b on the capacitive film 106 in the region Rcap, respectively.
As shown in FIG. 8(d), an n-type impurity is introduced into the p well 101 to form a source-drain region. Then, a layer insulating film 113, a contact hole 114 and a metal wiring layer 115 are successively formed. Thus, a semiconductor device in which the n-channel transistor and the two-layer polysilicon type capacitive element are provided is manufactured.
However, the capacitive film of the capacitive element is formed at the steps shown in FIGS. 8(a) to 8(d) simultaneously with the formation of the gate oxide film of the MOS transistor. For this reason, the capacitance value per unit area is defined by the material and the thickness of the gate oxide film. Since the capacitance value per unit area of the silicon oxide film is small, it is difficult to increase only the capacitance value per unit area of the capacitive film of the capacitive element. In addition, the capacitive film is formed by the oxidation of the polysilicon. The speed at which the polysilicon is oxidized is higher than the speed at which a silicon single crystal is oxidized. Consequently, the thickness of the capacitive film is much greater than that of the gate oxide film. Accordingly, the capacitance value per unit area of the capacitive film becomes small. For this reason, it is difficult to reduce the occupied area.
Also in e case where two-layer polysilicon is used, the gate oxide film and the capacitive film of the capacitive element can be formed of an insulating film having a different material as a method other than the method shown in FIGS. 8(a) to 8(d). In this case, a silicon nitride film which is separately deposited in place of the oxide film is patterned to be the capacitive film 106 in the state shown in FIG. 8(c). At this time, the capacitance value per unit area is not defined by the material and the thickness of the gate oxide film. Consequently, it is possible to reduce the occupied area. However, it is necessary to separately add the step of forming an etching mask for patterning the silicon nitride film. For this reason, the number of manufacturing steps is increased so that the whole manufacturing cost is raised.
As a variant of the above-mentioned method, there is also a method in which a gate oxide film is formed, a conductor film is deposited as the gate electrode of a transistor and the lower capacitive electrode of a capacitive element, and a silicon nitride film or the like is formed on the conductor film. A conductor film on which a silicide film having a low resistance is laminated is used for the gate electrode. However, in the case where the silicide film or the like is used for the lower capacitive electrode, the voltage withstanding properties and the reliability of the capacitive film formed on the lower capacitive electrode are deteriorated. It is also considered that a silicon nitride film or the like is deposited on the first conductor film 103 a in advance in the state shown in FIG. 8(b). In this case, the silicon nitride film is oxidized when forming the gate oxide film. Consequently, the capacitance value per unit area of the capacitive film is finally reduced.
Furthermore, the following method has also been known well. More specifically, a surface concentration in the vicinity of the gate oxide film of a well of a MOS transistor is controlled to form a MOS transistor of a depression type and a capacitive element made of the gate oxide film is formed simultaneously. In this method, the number of manufacturing steps is hardly increased. However, the capacitance value per unit area is comparatively small so that the area occupied by the capacitive element is increased. Consequently, it is hard to obtain high integration. In addition, the voltage dependency of the capacitance value is increased. For this reason, it is impossible to obtain the precision necessary for the use in an analog circuit.
As described above, the above-mentioned methods have merits and demerits. A device which can meet general requirements such as quality, a reduction in the area and manufacturing cost has not been made for practical use. Also in an analog-digital LSI, more fineness and higher integration have been demanded. Referring to an analog portion, the process for effectively reducing the area and the number of manufacturing steps at the same time has not been proposed and should be developed in order to realize the integration of the analog-digital LSI.
In the prior art, a resistive element is formed of a conductor film (a sheet resistance of 30 to 100 xcexa9/xe2x96xa1) which is obtained by introducing an impurity into polysilicon by the POC13 diffusion method or an ion implantation method. A conductor film having a low resistance (a sheet resistance of 5 to 10 xcexa9/xe2x96xa1) such as polycide which is formed by a lamination of polysilicon and silicide has been used for a gate electrode in such a manner that it can also be used for a local wiring. However, in the case where a certain resistance value is obtained in the resistive element, a conductor film having a is comparatively high resistance value should be used as a resistive film in order to reduce the area of the resistive element. For this reason, it is necessary to form a conductor film as the gate electrode by using a material having a low resistance and to form a conductor film as the resistive film by using a material having a comparatively high resistance without increasing the number of steps.
It is an object of the present invention to reduce the areas occupied by a capacitive element and a resistive element and to prevent an increase in cost caused by increasing the number of manufacturing steps in a semiconductor device in which two of a transistor, a capacitive element and a resistive element are provided.
The present invention provides a first semiconductor device in which at least a MIS transistor and a capacitive element are provided on a semiconductor substrate. The MIS transistor includes at least a gate insulating film formed on the semiconductor substrate, and a gate electrode formed of a first conductor film and a second conductor film which are laminated on the gate insulating film. The capacitive element includes a lower capacitive electrode formed of the first conductor film, a capacitive film formed on the lower capacitive electrode and made of an insulating film whose material is different from that of the gate insulating film, and an upper capacitive electrode formed on the capacitive film and made of the second conductor film.
According to such a structure, the lower capacitive electrode and the upper capacitive electrode of the capacitive element are formed of the first and second conductor films forming the gate electrode of the MIS transistor. Consequently, the first and second conductor films are patterned so that the gate electrode of the MIS transistor and each electrode of the capacitive element can be formed at the same time. More specifically, it is sufficient that a masking step to form the capacitive film is added as compared with a semiconductor device in which only the MIS transistor is provided. Furthermore, the capacitive film of the capacitive element is made of the insulating film having the material which is different from that of the gate insulating film of the MIS transistor. Consequently, the material having a high capacitance value per unit area can be used so that the area occupied by the capacitive element can be reduced. Accordingly, the semiconductor device in which the MIS transistor and the capacitive element having the small occupied area are provided can be obtained at low cost by using the two-layer polysilicon process.
The present invention provides a second semiconductor device in which at least a MIS transistor and a resistive element are provided on a semiconductor substrate. The MIS transistor includes at least a gate insulating film formed on the semiconductor substrate, and a gate electrode formed of a first conductor film and a second conductor film which are laminated on the gate insulating film. The resistive element includes a resistive film made of the first conductor film, an etching protection film formed in a region other than both ends of the resistive film and made of an insulating film whose material is different from that of the gate insulating film, and two leading electrodes formed over a portion from both ends of the etching protection film to the resistive film on the outside thereof, and made of the second conductor film.
According to such a structure, the etching protection film is formed on the resistive film of the resistive element. Consequently, the leading electrodes on both ends of the resistive film and the resistive film of the resistive element can be etched at the same time. In addition, the first and second conductor films forming the gate electrode of the MIS transistor are formed of the conductor film which is common to the resistive film and the leading electrodes of the resistive element. Consequently, the first and second conductor films are patterned so that the gate electrode of the MIS transistor, and the resistive film and the leading electrodes of the resistive element can be formed at the same time. More specifically, it is sufficient that a masking step to form the etching protection film is added as compared with a semiconductor device in which only the MIS transistor is provided. Furthermore, the gate electrode of the transistor has a two-layer structure. For this reason, if the resistance value of the second conductor film which is an upper layer is decreased, the resistance value of the first conductor film which is a lower layer may be increased. Consequently, the resistivity of the resistive element formed of the first conductor film can be increased so that the area occupied by the resistive element can be reduced. Accordingly, the semiconductor device in which the MIS transistor and the resistive element having the small occupied area are provided can be obtained at low cost by using the two-layer polysilicon process.
The present invention provides a third semiconductor device in which at least a capacitive element and a resistive element are provided on a semiconductor substrate. The capacitive element includes a lower capacitive electrode formed on the semiconductor substrate and made of a first conductor film, a capacitive film formed on the lower capacitive electrode and made of an insulating film, and an upper capacitive electrode formed on the capacitive film and made of the second conductor film. The resistive element includes a resistive film made of the first conductor film, an etching protection film formed on the resistive film and made of an insulating film which is common to the capacitive film of the capacitive element, and two leading electrodes formed over a portion from both ends of the etching protection film to the resistive film on the outside thereof, and made of the second conductor film.
According to such a structure, the etching protection film on the resistive film of the resistive element is formed of the insulating film which is common to the capacitive film of the capacitive element. Consequently, the leading electrodes on both ends of the resistive film and the resistive film of the resistive element can be etched at the same time. In addition, the upper capacitive electrode and the lower capacitive electrode of the capacitive element can be formed at the same time. Consequently, the number of necessary steps can be reduced. In addition, the areas occupied by the capacitive element and the resistive element can be reduced by the above-mentioned functions. Accordingly, the semiconductor device in which the capacitive element and the resistive element having the small occupied areas are provided can be obtained at low cost.
The present invention provides a fourth semiconductor device, in which the first semiconductor device further comprises a resistive element, the resistive element including a resistive film made of the first conductor film, an etching protection film formed on the resistive film and made of an insulating film which is common to the capacitive film of the capacitive element, and two leading electrodes formed over a portion from both ends of the etching protection film to the resistive film on the outside thereof, and made of the second conductor film.
According to such a structure, the above-mentioned functions can also be obtained and the semiconductor device in which the MIS transistor, the capacitive element and the resistive element are provided can be obtained at low cost.
In the first to fourth semiconductor devices, it is preferable that the insulating film should be made of at least one of a silicon nitride film, PZT and a tantalum oxide film.
According to such a structure, it is possible to obtain the capacitive film having a high capacitance value per unit area, and the etching protection film having the high function as the etching stoppers of the first and second conductor films.
The first to fourth semiconductor devices can further comprise an EEPROM memory cell, the EEPROM memory cell including a floating gate electrode formed of the first conductor film, an insulating film on a floating gate made of the insulating film, and a control gate electrode formed on the insulating film on the floating gate, and made of the second conductor film.
According to such a structure, it is possible to obtain the semiconductor device which has applicability enlarged and high functionality.
The present invention provides a first method for manufacturing a semiconductor device in which a capacitive element is provided on a semiconductor substrate, comprising the steps of depositing a first conductor film on the semiconductor substrate intervened by an insulating member, depositing an insulating film on the first conductor film, patterning the insulating film to form a capacitive film of the capacitive element, depositing a second conductor film on the insulating film and the first conductor film, and patterning the first and second conductor films by using an etching mask including at least a part of the capacitive film to form an upper capacitive electrode of the capacitive element by the second conductor film and to form a lower capacitive electrode of the capacitive element by the first conductor film.
According to such a method, the upper and lower capacitive electrodes can simultaneously be formed of the first and second conductor films by using the same etching mask, respectively. Also in the case where the MIS transistor is formed on the same substrate, the gate electrode can be formed by using the first and second conductor films. In addition, the capacitive film is formed on the first conductor film. Consequently, also in the case where the MIS transistor is formed on the same substrate, the step of forming a capacitive film is performed independently of the step of oxidizing a gate. Consequently, the resistive film can be formed by using a material having a high capacitance value per unit area as required. Accordingly, the step of forming a capacitive element can be incorporated by adding a few steps to the process for manufacturing a semiconductor device in which the MIS transistor is provided. Thus, it is possible to obtain the basic process for forming the capacitive element to provide the capacitive element having the small occupied area and various elements together at low cost.
In the first method for manufacturing a semiconductor device, the step of forming the upper capacitive electrode and the lower capacitive electrode is performed by using, as etching masks, a resist film having at least a first region which covers the predetermined region of the capacitive film and a second region which covers a region from an end of the capacitive film to the outside thereof, and the capacitive film to form the upper capacitive electrode made of the second conductor film which is left in the lower portion of the first region, a leading electrode of the lower capacitive electrode made of the second conductor film which is left in the lower portion of the second region, and the lower capacitive electrode made of the first conductor film which is left over a region covered with at least one of the capacitive film and the resist film.
According to such a method, the lower capacitive electrode, the upper capacitive electrode and the leading electrode can simultaneously be formed of the first and second conductor films by etching using the resist film and the capacitive film as etching masks, and it is very easy to realize a reduction in the masking steps and the formation of the capacitive element having the small occupied area.
The present invention provides a second method for manufacturing a semiconductor device in which a resistive element is provided on a semiconductor substrate, comprising the steps of depositing a first conductor film on the semiconductor substrate through an insulating member, depositing an insulating film on the first conductor film, patterning the insulating film to form an etching protection film, depositing a second conductor film on the etching protection film and the first conductor film, and forming a resistive film made of the first conductor film which is left over a region covered with either of the etching protection film and a resist film and forming a leading electrode of the resistive film made of the second conductor film which is left in a region covered with only the resist film by using, as etching masks, the etching protection film and the resist film having two regions which cover a region from both ends of the etching protection film to the outside thereof on the second conductor film.
According to such a method, the resistive film and the leading electrode of the resistive element are simultaneously formed at the steps of etching the first and second conductor films, and the resistive element is formed at a small number of steps. In addition, the resistive film having a small variation in the resistance value is formed because it is covered with the etching protection film when forming the resistive element. Thus, characteristics can be enhanced. Accordingly, it is possible to obtain the basic process for manufacturing the resistive element suitable for the process for the MIS transistor and the like in which the resistive element having excellent characteristics can be manufactured at a smaller number of steps.
The first or second method for manufacturing a semiconductor device can further comprise the step of forming a gate insulating film in an active region of the semiconductor substrate prior to the step of depositing a first conductor film, wherein the first conductor film is deposited also on the gate insulating film at the step of depositing a first conductor film, the insulating film in the active region is removed at the step of patterning an insulating film, the second conductor film is laminated on the first conductor film in the active region at the step of depositing a second conductor film, and a gate electrode made of the first and second conductor films is formed in the active region at the step of patterning the first and second conductor films.
According to such a method, a few masking steps are added to the steps of forming the MIS transistor so that the capacitive element, the resistive element and the MIS transistor are provided on the same semiconductor substrate by the above-mentioned manufacturing method. In particular, the resistive film of the resistive element and the lower layer of the gate electrode of the MIS transistor can be formed of the first conductor film having a high resistance value, and the leading electrode of the resistive element and the upper layer of the gate electrode of the MIS transistor can be formed of the second conductor film having a low resistance value. In addition, etching for patterning the insulating film is performed with the whole semiconductor substrate covered with the first conductor film. Consequently, there is little possibility that the active region of the MIS transistor is contaminated at the etching step. Accordingly, it is possible to manufacture the semiconductor device at low cost in which the capacitive element having the small occupied area, the resistive element having the small occupied area and high characteristics, and the MIS transistor having excellent characteristics are provided.
Furthermore, a part of the insulating film in a part of the active region can be left as an insulating film on a floating gate of an EEPROM at the step of patterning an insulating film, the second conductor film can be laminated on the first conductor film and the insulating film on the floating gate in the part of the active region at the step of depositing a second conductor film, and a control gate electrode of the EEPROM made of the second conductor film which is left below the resist film can be formed by using the resist film which covers a part of the insulating film on the floating gate and a floating gate electrode of the EEPROM made of the first conductor film which is left below the insulating film on the floating gate in the part of the active region at the step of patterning the first and second conductor films. According to such a method, the memory cell of the EEPROM is formed in the semiconductor device simultaneously with the formation of the MIS transistor, the capacitive element, the resistive element and the like. In addition, the special masking step of forming each element of the memory cell of the EEPROM is not necessary. Accordingly, it is possible to manufacture the EEPROM at low cost in which the capacitive element and the resistive element having the small occupied areas are provided.
The first or second method for manufacturing a semiconductor device can further comprise, prior to the step of patterning the insulating film, the steps of forming an element isolating trench by sequentially removing the insulating film, the first conductor film and the semiconductor substrate in a region where an element isolation is to be formed, depositing an insulating film for the element isolation which fills in the element isolating trench and covers the insulating film, and planarizing the insulating film for the element isolation by using the insulating film as a mask.
According to such a method, the element isolating trench having a trench isolation structure is formed by using, as an etching stopper, the insulating film to be the capacitive film of the capacitive element and the resistive film of the resistive element. By adding a few steps, thus, the element isolation having the trench structure with the high element isolating function can be formed on the semiconductor device in which the capacitive element, the resistive element, the MIS transistor, the memory cell of the EEPROM and the like are provided.